/*********************************************************************/

/* Copyright 2009, 2010 The University of Texas at Austin.           */

/* All rights reserved.                                              */

/*                                                                   */

/* Redistribution and use in source and binary forms, with or        */

/* without modification, are permitted provided that the following   */

/* conditions are met:                                               */

/*                                                                   */

/*   1. Redistributions of source code must retain the above         */

/*      copyright notice, this list of conditions and the following  */

/*      disclaimer.                                                  */

/*                                                                   */

/*   2. Redistributions in binary form must reproduce the above      */

/*      copyright notice, this list of conditions and the following  */

/*      disclaimer in the documentation and/or other materials       */

/*      provided with the distribution.                              */

/*                                                                   */

/*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */

/*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */

/*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */

/*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */

/*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */

/*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */

/*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */

/*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */

/*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */

/*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */

/*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */

/*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */

/*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */

/*    POSSIBILITY OF SUCH DAMAGE.                                    */

/*                                                                   */

/* The views and conclusions contained in the software and           */

/* documentation are those of the authors and should not be          */

/* interpreted as representing official policies, either expressed   */

/* or implied, of The University of Texas at Austin.                 */

/*********************************************************************/

#define ASSEMBLER

#include "common.h"

#define SP	r12

#define M	r32

#define N	r33

#define A	r36

#define LDA	r37

#define X	r38

#define INCX	r39

#define Y	r34

#define INCY	r35

#define BUFFER	r11

#define I	r14

#define J	r15

#define AO1	r16

#define AO2	r17

#define AO3	r18

#define AO4	r19

#define AO5	r20

#define AO6	r21

#define AO7	r22

#define AO8	r23

#define YLD1	r24

#define YST1	r25

#define YST2	r27

#define MM	r28

#define YY	r9

#define RPRE1	loc0

#define RPRE2	loc1

#define RPRE3	loc2

#define RPRE4	loc3

#define RPRE5	loc4

#define RPRE6	loc5

#define RPRE7	loc6

#define RPRE8	loc7

#define AO11	loc8

#define AO21	loc9

#define AO31	loc10

#define AO41	loc11

#define AO51	loc12

#define AO61	loc13

#define AO71	loc14

#define AO81	loc15

#define PREB	r8

#define ARLC	r29

#define PR	r30

#define ARPFS	r31

#ifdef DOUBLE

#define RPREFETCH	(16 * 3 +  8)

#else

#define RPREFETCH	(16 * 3 + 16)

#endif

#define PREFETCH	lfetch.nt1

#define ALPHA	f6

	PROLOGUE

	.prologue

	PROFCODE

	{ .mmi

	.save	ar.pfs, ARPFS

	alloc	ARPFS = ar.pfs, 8, 16, 8, 0

	mov	ARLC  = ar.lc

	}

	;;

	mov	PR = pr

	adds	r14 = 16, SP

	adds	r15 = 24, SP

	adds	r16 = 32, SP

	;;

	adds	r8 = -8 * 16, SP

	adds	r9 = -7 * 16, SP

	adds	SP = -8 * 16, SP

	;;

	stf.spill  [r8] = f16, 32

	stf.spill  [r9] = f17, 32

	;;	

	stf.spill  [r8] = f18, 32

	stf.spill  [r9] = f19, 32

	;;	

	stf.spill  [r8] = f20, 32

	stf.spill  [r9] = f21, 32

	;;

	stf.spill  [r8] = f22

	stf.spill  [r9] = f23

	.body

	;;	

	ld8	Y      = [r14]

	ld8	INCY   = [r15]

	ld8	BUFFER = [r16]

	mov	ALPHA = f8

	cmp.ge	p7, p0 = 0, M

	cmp.ge	p6, p0 = 0, N

	;;

	shladd	INCX = INCX, BASE_SHIFT, r0

	shladd	LDA  = LDA,  BASE_SHIFT, r0

	shladd	INCY = INCY, BASE_SHIFT, r0

	;;

	tbit.nz	p8, p0 = A,   BASE_SHIFT

	tbit.nz	p9, p0 = LDA, BASE_SHIFT

	mov	MM  = M

	;;

	(p8) adds MM = -1, M

	;;

	(p7) br.cond.dpnt .L999

	(p6) br.cond.dpnt .L999

	;;

	sub	I = A, Y

	cmp.eq	p10, p0 = SIZE, INCY

	mov	YY = Y

	;;

	(p10) tbit.z.unc p10, p0 = I, BASE_SHIFT

	;;

	(p10) br.cond.dptk .L10

	;;

	shr	J = M, 3

	mov	YY = BUFFER

	;;

	(p8) adds  YY = SIZE, BUFFER

	;;

	mov	ar.lc = J

	mov	YST1 = YY

	adds	YST2 = 4 * SIZE, YY

	;;

.L02:

	STFD	[YST1] = f0, 1 * SIZE

	STFD	[YST2] = f0, 1 * SIZE

	;;

	STFD	[YST1] = f0, 1 * SIZE

	STFD	[YST2] = f0, 1 * SIZE

	;;

	STFD	[YST1] = f0, 1 * SIZE

	STFD	[YST2] = f0, 1 * SIZE

	;;

	STFD	[YST1] = f0, 5 * SIZE

	STFD	[YST2] = f0, 5 * SIZE

	br.cloop.sptk.few .L02

	;;

.L10:

	{ .mib

	nop   __LINE__

	shr	J   = N, 3

	(p9)	br.cond.dptk	.L100

	}

	;;

	{ .mib

	nop   __LINE__

	cmp.eq	p6, p0 = r0, J

	(p6) br.cond.dpnt .L20

	}

	;;

	.align 16

.L11:

	mov	YLD1 = YY

	mov	YST1 = YY

	adds	YST2 = 4 * SIZE, YY

	;;

	LDFD	f8 = [X], INCX

	;;

	LDFD	f9 = [X], INCX

	;;

	LDFD	f10 = [X], INCX

	;;

	LDFD	f11 = [X], INCX

	;;

	LDFD	f12 = [X], INCX

	;;

	LDFD	f13 = [X], INCX

	;;

	LDFD	f14 = [X], INCX

	;;

	LDFD	f15 = [X], INCX

	;;

	FMPY	f8  = ALPHA, f8

	FMPY	f9  = ALPHA, f9

	FMPY	f10 = ALPHA, f10

	FMPY	f11 = ALPHA, f11

	FMPY	f12 = ALPHA, f12

	FMPY	f13 = ALPHA, f13

	FMPY	f14 = ALPHA, f14

	FMPY	f15 = ALPHA, f15

	;;

	mov	AO1 = A

	add	AO2 = LDA, A

	;;

	shladd	AO3 = LDA, 1, A

	shladd	AO4 = LDA, 1, AO2

	;;

	shladd	AO5 = LDA, 1, AO3

	shladd	AO6 = LDA, 1, AO4

	;;

	shladd	AO7 = LDA, 1, AO5

	shladd	AO8 = LDA, 1, AO6

	shladd	A   = LDA, 3, A

	;;

	;;

	adds	PREB   = RPREFETCH * SIZE, YLD1

	adds	RPRE1  = RPREFETCH * SIZE, AO1

	adds	RPRE2  = (RPREFETCH + 8) * SIZE, AO2

	adds	RPRE3  = RPREFETCH * SIZE, AO3

	adds	RPRE4  = (RPREFETCH + 8) * SIZE, AO4

	adds	RPRE5  = RPREFETCH * SIZE, AO5

	adds	RPRE6  = (RPREFETCH + 8) * SIZE, AO6

	adds	RPRE7  = RPREFETCH * SIZE, AO7

	adds	RPRE8  = (RPREFETCH + 8) * SIZE, AO8

	(p8) LDFD	f80 = [AO1], 1 * SIZE

	(p8) LDFD	f81 = [AO2], 1 * SIZE

	(p8) LDFD	f82 = [AO3], 1 * SIZE

	(p8) LDFD	f83 = [AO4], 1 * SIZE

	(p8) LDFD	f84 = [AO5], 1 * SIZE

	(p8) LDFD	f85 = [AO6], 1 * SIZE

	(p8) LDFD	f86 = [AO7], 1 * SIZE

	(p8) LDFD	f87 = [AO8], 1 * SIZE

	(p8) LDFD	f106 = [YLD1], 1 * SIZE

	;;

	(p8) FMPY	f32 = f8,  f80

	(p8) FMPY	f33 = f9,  f81

	(p8) FMPY	f34 = f10, f82

	(p8) FMA	f35 = f11, f83, f106

	;;

	(p8) FMA	f32 = f12, f84, f32

	(p8) FMA	f33 = f13, f85, f33

	(p8) FMA	f34 = f14, f86, f34

	(p8) FMA	f35 = f15, f87, f35

	;;

	(p8) FADD	f32 = f32, f33

	(p8) FADD	f34 = f34, f35

	;;

	(p8) FADD	f32 = f32, f34

	;;

	(p8) STFD	[YST1] = f32, 1 * SIZE

	(p8) adds	YST2 = 1 * SIZE, YST2

	;;

	shr	I = MM, 3

	mov	pr.rot= 0

	;;

	cmp.eq	p6, p0 = 0, I

	cmp.eq	p16, p0 = r0, r0

	;;

	adds	I = -1, I

	tbit.nz	p13, p0 = MM, 2

	;;

	mov	ar.lc = I

	mov	ar.ec = 2

	(p6) br.cond.dpnt .L15

	;;

	.align 16

.L12:

	{ .mmf

 	(p18) STFD	[YST1] = f16, 1 * SIZE

	(p18) STFD	[YST2] = f17, 1 * SIZE

	(p17) FMA	f16 = f8,  f33, f101

	}

	{ .mfi

	(p17) LDFPD	f93,  f94  = [AO8], 2 * SIZE

	(p17) FMA	f17 = f8,  f37, f113

	(p16) tbit.nz.unc p14, p15 = I, 0

	}

	;;

	{ .mmf

	(p18) STFD	[YST1] = f18, 1 * SIZE

	(p18) STFD	[YST2] = f19, 1 * SIZE

	(p17) FMA	f18 = f8,  f34, f104

	}

	{ .mmf

	(p14) lfetch.excl.nt1	[PREB],  16 * SIZE

	(p17) LDFPD	f95,  f96  = [AO8], 2 * SIZE

	(p17) FMA	f19 = f8,  f38, f116

	}

	;;

	{ .mmf

	(p18) STFD	[YST1] = f20, 1 * SIZE

	(p18) STFD	[YST2] = f21, 1 * SIZE

	(p17) FMA	f20 = f8,  f35, f107

	}

	{ .mfi

	(p16) LDFPD	f32,  f33  = [AO1], 2 * SIZE

	(p17) FMA	f21 = f8,  f39, f119

	nop   __LINE__

	}

	;;

	{ .mmf

	(p18) STFD	[YST1] = f22, 5 * SIZE

	(p18) STFD	[YST2] = f23, 5 * SIZE

	(p17) FMA	f22 = f8,  f36, f110

	}

	{ .mmf

	(p16) LDFPD	f34,  f35  = [AO1], 2 * SIZE

	(p16) LDFPD	f100, f103 = [YLD1], 2 * SIZE

	(p17) FMA	f23 = f8,  f40, f122

	}

	;;

	{ .mmf

	(p14) PREFETCH	[RPRE1], 16 * SIZE

	(p16) LDFPD	f36,  f37  = [AO1], 2 * SIZE

	(p17) FMA	f16 = f9,  f41, f16

	}

	{ .mfi

	(p16) LDFPD	f106, f109 = [YLD1], 2 * SIZE

	(p17) FMA	f17 = f9,  f45, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f38,  f39  = [AO1], 2 * SIZE

	(p17) FMA	f18 = f9,  f42, f18

	nop   __LINE__

	}

	{ .mfi

	(p16) LDFPD	f112, f115 = [YLD1], 2 * SIZE

	(p17) FMA	f19 = f9,  f46, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f40,  f41  = [AO2], 2 * SIZE

	(p17) FMA	f20 = f9,  f43, f20

	nop   __LINE__

	}

	{ .mfi

	(p16) LDFPD	f118, f121 = [YLD1], 2 * SIZE

	(p17) FMA	f21 = f9,  f47, f21

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f42,  f43  = [AO2], 2 * SIZE

	(p17) FMA	f22 = f9,  f44, f22

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f9,  f48, f23

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f44,  f45  = [AO2], 2 * SIZE

	(p17) FMA	f16 = f10, f49, f16

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f10, f53, f17

	nop   __LINE__

	}

	;;

	{ .mmf

	(p15) PREFETCH	[RPRE2], 16 * SIZE

	(p16) LDFPD	f46,  f47  = [AO2], 2 * SIZE

	(p17) FMA	f18 = f10, f50, f18

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f10, f54, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f48,  f49  = [AO3], 2 * SIZE

	(p17) FMA	f20 = f10, f51, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f10, f55, f21

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f50,  f51  = [AO3], 2 * SIZE

	(p17) FMA	f22 = f10, f52, f22

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f10, f56, f23

	nop   __LINE__

	}

	;;

	{ .mmf

	(p14) PREFETCH	[RPRE3], 16 * SIZE

	(p16) LDFPD	f52,  f53  = [AO3], 2 * SIZE

	(p17) FMA	f16 = f11, f57, f16

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f11, f61, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f54,  f55  = [AO3], 2 * SIZE

	(p17) FMA	f18 = f11, f58, f18

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f11, f62, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f56,  f57  = [AO4], 2 * SIZE

	(p17) FMA	f20 = f11, f59, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f11, f63, f21

	nop   __LINE__

	}

	;;

	{ .mmf

	(p15) PREFETCH	[RPRE4], 16 * SIZE

	(p16) LDFPD	f58,  f59  = [AO4], 2 * SIZE

	(p17) FMA	f22 = f11, f60, f22

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f11, f64, f23

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f60,  f61  = [AO4], 2 * SIZE

	(p17) FMA	f16 = f12, f65, f16

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f12, f69, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f62,  f63  = [AO4], 2 * SIZE

	(p17) FMA	f18 = f12, f66, f18

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f12, f70, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f64,  f65  = [AO5], 2 * SIZE

	(p17) FMA	f20 = f12, f67, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f12, f71, f21

	nop   __LINE__

	}

	;;

	{ .mmf

 	(p14) PREFETCH	[RPRE5], 16 * SIZE

	(p16) LDFPD	f66,  f67  = [AO5], 2 * SIZE

	(p17) FMA	f22 = f12, f68, f22

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f12, f72, f23

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f68,  f69  = [AO5], 2 * SIZE

	(p17) FMA	f16 = f13, f73, f16

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f13, f77, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f70,  f71  = [AO5], 2 * SIZE

	(p17) FMA	f18 = f13, f74, f18

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f13, f78, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f72,  f73  = [AO6], 2 * SIZE

	(p17) FMA	f20 = f13, f75, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f13, f79, f21

	nop   __LINE__

	}

	;;

	{ .mmf

	(p15) PREFETCH	[RPRE6], 16 * SIZE

	(p16) LDFPD	f74,  f75  = [AO6], 2 * SIZE

	(p17) FMA	f22 = f13, f76, f22

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f13, f80, f23

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f76,  f77  = [AO6], 2 * SIZE

	(p17) FMA	f16 = f14, f81, f16

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f14, f85, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f78,  f79  = [AO6], 2 * SIZE

	(p17) FMA	f18 = f14, f82, f18

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f14, f86, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f80,  f81  = [AO7], 2 * SIZE

	(p17) FMA	f20 = f14, f83, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f14, f87, f21

	nop   __LINE__

	}

	;;

	{ .mmf

	(p14) PREFETCH	[RPRE7], 16 * SIZE

	(p16) LDFPD	f82,  f83  = [AO7], 2 * SIZE

	(p17) FMA	f22 = f14, f84, f22

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f23 = f14, f88, f23

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f84,  f85  = [AO7], 2 * SIZE

	(p17) FMA	f16 = f15, f89, f16

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f17 = f15, f93, f17

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f86,  f87  = [AO7], 2 * SIZE

	(p17) FMA	f18 = f15, f90, f18

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f19 = f15, f94, f19

	nop   __LINE__

	}

	;;

	{ .mfi

	(p16) LDFPD	f88,  f89  = [AO8], 2 * SIZE

	(p17) FMA	f20 = f15, f91, f20

	nop   __LINE__

	}

	{ .mfi

	nop   __LINE__

	(p17) FMA	f21 = f15, f95, f21

	(p16) adds	I = -1, I

	}

	;;

	{ .mmf

	(p15) PREFETCH	[RPRE8], 16 * SIZE

	(p16) LDFPD	f90,  f91  = [AO8], 2 * SIZE

	(p17) FMA	f22 = f15, f92, f22

	}

	{ .mfb

	nop   __LINE__

	(p17) FMA	f23 = f15, f96, f23

	br.ctop.sptk.few .L12

	}

	;;

	.align 16

.L15:

	{ .mmi

 	(p18) STFD	[YST1] = f16, 1 * SIZE

	(p18) STFD	[YST2] = f17, 1 * SIZE

	tbit.nz	p14, p0 = MM, 1

	}

	{ .mmi

	(p13) LDFPD	f32,  f33  = [AO1], 2 * SIZE

	(p13) LDFPD	f100, f101 = [YLD1], 2 * SIZE

	cmp.lt p6, p0 = 1, J

	}

	;;

	{ .mmi

	(p18) STFD	[YST1] = f18, 1 * SIZE

	(p18) STFD	[YST2] = f19, 1 * SIZE

	tbit.nz	p15, p0 = MM, 0

	}

	{ .mmi

	(p13) LDFPD	f48,  f49  = [AO1], 2 * SIZE

	(p13) LDFPD	f102, f103 = [YLD1], 2 * SIZE

	adds J = -1, J

	}

	;;

	{ .mmi

	(p18) STFD	[YST1] = f20, 1 * SIZE

	(p18) STFD	[YST2] = f21, 1 * SIZE

	nop	__LINE__

	}

	{ .mmi

	(p14) LDFPD	f64,  f65  = [AO1], 2 * SIZE

	(p14) LDFPD	f104, f105 = [YLD1], 2 * SIZE

	nop	__LINE__

	}

	;;

	{ .mmi

	(p18) STFD	[YST1] = f22, 5 * SIZE

	(p18) STFD	[YST2] = f23, 5 * SIZE

	nop	__LINE__

	}

	{ .mmi

	(p13) LDFPD	f34,  f35  = [AO2], 2 * SIZE

	(p13) LDFPD	f36,  f37  = [AO3], 2 * SIZE

	nop	__LINE__

	}

	;;

	{ .mmi

	(p15) LDFD	f80 = [AO1]

	(p15) LDFD	f106 = [YLD1], 1 * SIZE

	nop	__LINE__

	}

	{ .mmi

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mmi

	(p13) LDFPD	f50,  f51  = [AO2], 2 * SIZE

	(p13) LDFPD	f52,  f53  = [AO3], 2 * SIZE

	nop	__LINE__

	}

	{ .mmi

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mmi

	(p14) LDFPD	f66,  f67  = [AO2], 2 * SIZE

	(p14) LDFPD	f68,  f69  = [AO3], 2 * SIZE

	nop	__LINE__

	}

	{ .mmi

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mmi

	(p15) LDFD	f81 = [AO2]

	(p15) LDFD	f82 = [AO3]

	nop	__LINE__

	}

	{ .mmi

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f38,  f39  = [AO4], 2 * SIZE

	(p13) FMA	f100 = f8,  f32, f100

	nop	__LINE__

	}

	{ .mfi

	(p13) LDFPD	f40,  f41  = [AO5], 2 * SIZE

	(p13) FMA	f101 = f8,  f33, f101

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f54,  f55  = [AO4], 2 * SIZE

	(p13) FMA	f102 = f8,  f48, f102

	nop	__LINE__

	}

	{ .mfi

	(p13) LDFPD	f56,  f57  = [AO5], 2 * SIZE

	(p13) FMA	f103 = f8,  f49, f103

	nop	__LINE__

	}

	;;

	{ .mfi

	(p14) LDFPD	f70,  f71  = [AO4], 2 * SIZE

	(p14) FMA	f104 = f8,  f64, f104

	nop	__LINE__

	}

	{ .mfi

	(p14) LDFPD	f72,  f73  = [AO5], 2 * SIZE

	(p14) FMA	f105 = f8,  f65, f105

	nop	__LINE__

	}

	;;

	{ .mfi

	(p15) LDFD	f83 = [AO4]

	(p15) FMA	f106 = f8,  f80, f106

	nop	__LINE__

	}

	{ .mfi

	(p15) LDFD	f84 = [AO5]

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f42,  f43  = [AO6], 2 * SIZE

	(p13) FMA	f100 = f9,  f34, f100

	nop	__LINE__

	}

	{ .mfi

	(p13) LDFPD	f44,  f45  = [AO7], 2 * SIZE

	(p13) FMA	f101 = f9,  f35, f101

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f58,  f59  = [AO6], 2 * SIZE

	(p13) FMA	f102 = f9,  f50, f102

	nop	__LINE__

	}

	{ .mfi

	(p13) LDFPD	f60,  f61  = [AO7], 2 * SIZE

	(p13) FMA	f103 = f9,  f51, f103

	nop	__LINE__

	}

	;;

	{ .mfi

	(p14) LDFPD	f74,  f75  = [AO6], 2 * SIZE

	(p14) FMA	f104 = f9,  f66, f104

	nop	__LINE__

	}

	{ .mfi

	(p14) LDFPD	f76,  f77  = [AO7], 2 * SIZE

	(p14) FMA	f105 = f9,  f67, f105

	nop	__LINE__

	}

	;;

	{ .mfi

	(p15) LDFD	f85 = [AO6]

	(p15) FMA	f106 = f9,  f81, f106

	nop	__LINE__

	}

	{ .mfi

	(p15) LDFD	f86 = [AO7]

	nop	__LINE__

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f46,  f47  = [AO8], 2 * SIZE

	(p13) FMA	f100 = f10, f36, f100

	nop	__LINE__

	}

	{ .mfi

	(p13) FMA	f101 = f10, f37, f101

	nop	__LINE__

	}

	;;

	{ .mfi

	(p13) LDFPD	f62,  f63  = [AO8], 2 * SIZE

	(p13) FMA	f102 = f10, f52, f102

	nop	__LINE__

	}

	{ .mfi

	(p13) FMA	f103 = f10, f53, f103

	nop	__LINE__

	}

	;;

	{ .mfi

	(p14) LDFPD	f78,  f79  = [AO8], 2 * SIZE

	(p14) FMA	f104 = f10, f68, f104

	nop	__LINE__

	}

	{ .mfi

	(p14) FMA	f105 = f10, f69, f105

	nop	__LINE__

	}

	;;

	{ .mfi

	(p15) LDFD	f87 = [AO8]

	(p15) FMA	f106 = f10, f82, f106

	nop	__LINE__

	}

	;;

	(p13) FMA	f100 = f11, f38, f100

	(p13) FMA	f101 = f11, f39, f101

	(p13) FMA	f102 = f11, f54, f102

	(p13) FMA	f103 = f11, f55, f103

	(p14) FMA	f104 = f11, f70, f104

	(p14) FMA	f105 = f11, f71, f105

	(p15) FMA	f106 = f11, f83, f106

	;;

	(p13) FMA	f100 = f12, f40, f100

	(p13) FMA	f101 = f12, f41, f101

	(p13) FMA	f102 = f12, f56, f102

	(p13) FMA	f103 = f12, f57, f103

	(p14) FMA	f104 = f12, f72, f104

	(p14) FMA	f105 = f12, f73, f105