Blame thirdparty/openblas/xianyi-OpenBLAS-e6e87a2/kernel/power/zgemm_beta.S

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/*********************************************************************/
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/* Copyright 2009, 2010 The University of Texas at Austin.           */
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/* All rights reserved.                                              */
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/*                                                                   */
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/* Redistribution and use in source and binary forms, with or        */
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/* without modification, are permitted provided that the following   */
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/* conditions are met:                                               */
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/*                                                                   */
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/*   1. Redistributions of source code must retain the above         */
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/*      copyright notice, this list of conditions and the following  */
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/*      disclaimer.                                                  */
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/*                                                                   */
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/*   2. Redistributions in binary form must reproduce the above      */
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/*      copyright notice, this list of conditions and the following  */
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/*      disclaimer in the documentation and/or other materials       */
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/*      provided with the distribution.                              */
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/*                                                                   */
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/*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
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/*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
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/*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
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/*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
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/*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
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/*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
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/*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
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/*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
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/*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
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/*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
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/*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
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/*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
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/*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
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/*    POSSIBILITY OF SUCH DAMAGE.                                    */
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/*                                                                   */
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/* The views and conclusions contained in the software and           */
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/* documentation are those of the authors and should not be          */
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/* interpreted as representing official policies, either expressed   */
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/* or implied, of The University of Texas at Austin.                 */
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/*********************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define	M	r3
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#define	N	r4
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#define	C	r10
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#define	LDC	r11
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#define	J	r5
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#define PRE	r6
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#define	CO1	r7
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#define ALPHA_R	f30
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#define ALPHA_I	f31
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#define STACKSIZE 32
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	PROLOGUE
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	PROFCODE
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	addi	SP, SP, -STACKSIZE
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	li	r0, 0
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	stfd	f30,    0(SP)
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	stfd	f31,    8(SP)
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	stw	r0,    16(SP)
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#ifdef linux
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#ifndef __64BIT__
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	lwz	LDC,      8 + STACKSIZE(SP)
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#else
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	ld	C,      120 + STACKSIZE(SP)
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	ld	LDC,    128 + STACKSIZE(SP)
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#endif
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#endif
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#if defined(_AIX) || defined(__APPLE__)
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#ifdef __64BIT__
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	ld	C,      120 + STACKSIZE(SP)
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	ld	LDC,    128 + STACKSIZE(SP)
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#else
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#ifdef DOUBLE
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	lwz	C,       68 + STACKSIZE(SP)
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	lwz	LDC,     72 + STACKSIZE(SP)
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#else
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	lwz	C,       60 + STACKSIZE(SP)
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	lwz	LDC,     64 + STACKSIZE(SP)
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#endif
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#endif
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#endif
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	slwi	LDC, LDC, ZBASE_SHIFT
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	lfs	f0,    16(SP)
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	fmr	ALPHA_R, f1
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	fmr	ALPHA_I, f2
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	cmpwi	cr0, M, 0
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	ble-	LL(999)
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	cmpwi	cr0, N, 0
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	ble-	LL(999)
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	mr	J, N
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	fcmpu	cr7, f1, f0
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	bne	cr7, LL(20)
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	fcmpu	cr7, f2, f0
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	bne	cr7, LL(20)
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	.align 4
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LL(10):
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	mr	CO1, C
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	add	C,  C, LDC
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	addi	PRE, 0, 32 * SIZE
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	srawi.	r0,  M,  3
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	mtspr	CTR, r0
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	ble	LL(15)
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	.align 4
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LL(12):
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	STFD	f0,   0 * SIZE(CO1)
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	STFD	f0,   1 * SIZE(CO1)
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	STFD	f0,   2 * SIZE(CO1)
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	STFD	f0,   3 * SIZE(CO1)
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	STFD	f0,   4 * SIZE(CO1)
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	STFD	f0,   5 * SIZE(CO1)
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	STFD	f0,   6 * SIZE(CO1)
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	STFD	f0,   7 * SIZE(CO1)
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	STFD	f0,   8 * SIZE(CO1)
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	STFD	f0,   9 * SIZE(CO1)
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	STFD	f0,  10 * SIZE(CO1)
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	STFD	f0,  11 * SIZE(CO1)
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	STFD	f0,  12 * SIZE(CO1)
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	STFD	f0,  13 * SIZE(CO1)
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	STFD	f0,  14 * SIZE(CO1)
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	STFD	f0,  15 * SIZE(CO1)
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	dcbst	PRE, CO1
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	addi	CO1, CO1,  16 * SIZE
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	bdnz	LL(12)
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	.align 4
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LL(15):
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	andi.	r0,  M,  7
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	mtspr	CTR, r0
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	beq	LL(19)
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	.align 4
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LL(16):
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	STFD	f0,  0 * SIZE(CO1)
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	STFD	f0,  1 * SIZE(CO1)
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	addi	CO1, CO1, 2 * SIZE
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	bdnz	LL(16)
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	.align 4
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LL(19):
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	addic.	J,  J,  -1
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	bgt	LL(10)
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	b	LL(999)
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	.align 4
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LL(20):
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	mr	CO1, C
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	add	C,  C, LDC
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	addi	PRE, 0, 16 * SIZE
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	srawi.	r0,  M,  2
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	mtspr	CTR, r0
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	ble	LL(25)
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	.align 4
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LL(22):
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	LFD	f3,  0 * SIZE(CO1)
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	LFD	f4,  1 * SIZE(CO1)
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	LFD	f5,  2 * SIZE(CO1)
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	LFD	f6,  3 * SIZE(CO1)
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	LFD	f7,  4 * SIZE(CO1)
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	LFD	f8,  5 * SIZE(CO1)
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	LFD	f9,  6 * SIZE(CO1)
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	LFD	f10, 7 * SIZE(CO1)
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	FMUL	f0,  ALPHA_I, f4
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	FMUL	f4,  ALPHA_R, f4
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	FMUL	f11, ALPHA_I, f6
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	FMUL	f6,  ALPHA_R, f6
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	FMUL	f12, ALPHA_I, f8
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	FMUL	f8,  ALPHA_R, f8
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	FMUL	f13, ALPHA_I, f10
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	FMUL	f10, ALPHA_R, f10
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	FMADD	f4,  ALPHA_I, f3, f4
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	FMSUB	f3,  ALPHA_R, f3, f0
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	FMADD	f6,  ALPHA_I, f5, f6
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	FMSUB	f5,  ALPHA_R, f5, f11
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	FMADD	f8,  ALPHA_I, f7, f8
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	FMSUB	f7,  ALPHA_R, f7, f12
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	FMADD	f10, ALPHA_I, f9, f10
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	FMSUB	f9,  ALPHA_R, f9, f13
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	STFD	f3,  0 * SIZE(CO1)
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	STFD	f4,  1 * SIZE(CO1)
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	STFD	f5,  2 * SIZE(CO1)
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	STFD	f6,  3 * SIZE(CO1)
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	STFD	f7,  4 * SIZE(CO1)
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	STFD	f8,  5 * SIZE(CO1)
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	STFD	f9,  6 * SIZE(CO1)
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	STFD	f10, 7 * SIZE(CO1)
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	addi	CO1, CO1,  8 * SIZE
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	dcbtst	PRE, CO1
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	bdnz	LL(22)
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	.align 4
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LL(25):
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	andi.	r0,  M,  3
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	mtspr	CTR, r0
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	ble	LL(29)
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	.align 4
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LL(26):
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	LFD	f0,  0 * SIZE(CO1)
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	LFD	f1,  1 * SIZE(CO1)
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	FMUL	f5, ALPHA_I, f1
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	FMUL	f1, ALPHA_R, f1
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	FMADD	f1, ALPHA_I, f0, f1
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	FMSUB	f0, ALPHA_R, f0, f5
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	STFD	f0,  0 * SIZE(CO1)
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	STFD	f1,  1 * SIZE(CO1)
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	addi	CO1, CO1, 2 * SIZE
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	bdnz	LL(26)
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	.align 4
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LL(29):
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	addic.	J,  J,  -1
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	bgt	LL(20)
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	.align 4
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LL(999):
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	li	r3, 0
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	lfd	f30,    0(SP)
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	lfd	f31,    8(SP)
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	addi	SP, SP, STACKSIZE
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	blr
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	EPILOGUE